It has been considered an efficient usage in a computer system to employ flash EEPROMs which store application programs as auxiliary memories and are operable in conjunction with buses of main memories such as dynamic random access memories therein. One type of such Flash EEPROMs has been proposed by Intel Co. in October 1994, identified as Flash Memory 28F016xD, which is now referred to as DRAM-interface flash EEPROM because it includes a pin arrangement adaptable to interfacing with a DRAM. FIG. 1 shows the layout configuration of the pins of Intel's device, being comprised of data input/output pins DQ0-DQ15, address input pins A0-A9, row address strobe pin RAS, column address strobe pin CAS, read protect pin RP, write protect pin WP and ready/busy pin RY/BY. RP places the flash memory into a sleep mode to minimize current dissipation when it is not activated. WP prevents the data stored in the memory from being lost during power-up and power-down periods. RY/BY allows other devices within a system to recognize a programming time or an erasure time of the flash memory.
As is well known, operations of a DRAM are determined by the states of the control signals such as write enable signal WE. A low level on WE activates a writing operation while a high level activates a read operation, just in the DRAM. On the other hand, a flash memory can only be initiated by setting commands by way of data input/output pins DQ0-DQ15. For example, commands FFh, 40h, 20h and 0Ch may enable a read mode, a writing mode, an erasure mode and a programming mode, respectively. In a read operation of the conventional device, as shown in FIG. 2, if a read command (e.g., FFh) is applied to DQ when WE, RAS and CAS are all at low levels, address signals A0-A9 applied to the device are ignored. RAS and CAS respectively read row and column addresses with both a flash memory and a DRAM. DQ is held at a high impedance until both addresses are completely received. Data is output from DQ when WE is at a high level.
FIG. 3 shows a writing operation of the flash memory, which is same as the read operation of FIG. 2 except for the command information and the logic status of WE. The operation for receiving the write command has the same timing as a normal DRAM writing operation. In the event the flash memory and the DRAM share buses, it can be seen from FIG. 3 that a writing operation for only the flash memory may cause the DRAM to perform an unwanted writing operation. Because of this fact, flash memory and DRAM cannot share buses, that is, they have to use their own individual buses.
In addition, considering that an entire flash memory writing operation, which generally consists of two steps: (1) the writing operation as shown in FIG. 3 in which external data are applied to and stored in page buffers; and (2) the programming cycle in which the data stored in the page buffers are written into flash memory cells, substantially corresponds to a DRAM writing operation, it can be understood that a further input cycle for issuing a programming command is needed after the writing cycle of FIG. 3. Thus, a central processor unit (CPU) has to carry out an additional operation for generating the programming command even though other works may be delayed, thereby causing degradation in system performance. And conventional controller chip-sets used only for the DRAMs must be modified because they must support the command-controlled flash memories, as well as the DRAMs.
FIG. 4 is a schematic illustrating a part of cell array in a conventional NAND type flash memory device, FIG. 5 illustrates a lay-out pattern of the NAND cell unit in FIG. 4, and FIG. 6 is a corss-sectional view taken along line I--I in FIG. 5.
Referring to FIGS. 4 through 6, gates of the cell transistors of NAND cell units NU are coupled to word lines WL1-WL7 and bit lines BL1-BLn are connected to the cell units. The higher the density and capacity of the memory get, the more the length of the word and bit lines is increased and then the more the parasitic capacitance and resistance are increased. Those parasitic demerits cause the random access time--the time from a selection of a word line to output of data through a bit line--to be longer and acts as a major limitation in designing a high speed flash memory.
As one way to enhance the access speed, a folded bit line sensing scheme, which is employed in DRAMS, has been proposed. However, since each sense amplifier is coupled between a pair of bit lines (one is a reference line) and a selected memory cell to be programmed is connected to just one of the bit line pair, the entire memory capacity might be reduced.
If, in order to increase the memory capacity, each of cross points between word lines and the pairs of bit lines is coupled to one memory cell, the data loading (or latching) operation for the pair of bit lines after a flash erasure against all memory cells is takes at least two cycles because only half of the memory cells can be programmed at one time. Thus, the whole programming time increases. Moreover, in case there are some data which need to be saved, the data must be read outside before an erasure and re-written after the erasure. Such management of the secured data is inconvenient when using the memory.
On the other hand, the architecture of a conventional memory cell array having lockable cells is shown in FIG. 7, in which an erasure lock function is equipped to protect data stored in memory cells from being destroyed by device malfunction due to the external noises and/or the abrupt changes in supply voltages. The lockable cells LM1-LM7 are arranged in correspondence with word lines WL0-WL7 and each lockable cell retains alternative information for an erasure lock and an erasure unlock for a corresponding page. If lockable cell LM1 is an off-cell, the page, memory cells coupled to WL0, is considered to be in an erasure lock state. To the contrary, LM1 of an on-cell indicates that the page is laid on an erasure unlock state, which means it is available to program the memory cells within the page. However, in programming and erasing the lockable cells, data stored in the memory cells have to be saved and re-written, before and after either programming or erasing the lockable cells, respectively.